Despre microcontroller-ul Intel 8051
INTEL 8051 (MCS-51) este a doua generatie de MC si, in prezent, este familia care se vinde cel mai bine; este fabricat si de multi alti producatori.
Acest MC are o arhitectura Harvard modificata cu spatiu de adresare diferit pentru program (<64K din care 4-8K pe chip) si date (<64K din care 128-256 octeti pe chip, cu adresare indirecta).
Dispozitivele I/O au un spatiu propriu de adresare. 8051 dispune de un procesor boolean prin care se pot executa operatii complexe la nivel de bit, iar in functie de rezultate, se pot face salturi.
Pentru 8051 exista foarte mult software, atat contra cost cat si gratuit.
Structura cursului
Seminar 1: A flexible scheduler for single-processor embedded systems
- Overview of this seminar
- Overview of this course
- By the end of the course you’ll be able to …
- Main course text
- IMPORTANT: Course prerequisites
- Review: Why use C?
- Review: The 8051 microcontroller
- Review: The „super loop” software architecture
- Review: An introduction to schedulers
- Review: Building a scheduler
- Overview of this seminar
- The Co-operative Scheduler
- Overview
- The scheduler data structure and task array
- The size of the task array
- One possible initialisation function:
- IMPORTANT: The ‘one interrupt per microcontroller’ rule!
- The ‘Update’ function
- The ‘Add Task’ function
- The ‘Dispatcher’
- Function arguments
- Function pointers and Keil linker options
- The ‘Start’ function
- The ‘Delete Task’ function
- Reducing power consumption
- Reporting errors
- Displaying error codes
- Hardware resource implications
- What is the CPU load of the scheduler?
- Determining the required tick interval
- Guidelines for predictable and reliable scheduling
- Overall strengths and weaknesses of the scheduler
- Preparations for the next seminar
Seminar 2: A closer look at co-operative task scheduling (and some alternatives)
- Overview of this seminar
- Review: Co-operative scheduling
- The pre-emptive scheduler
- Why do we avoid pre-emptive schedulers in this course?
- Why is a co-operative scheduler (generally) more reliable?
- Critical sections of code
- How do we deal with critical sections in a pre-emptive system?
- Building a „lock” mechanism
- The „best of both worlds” – a hybrid scheduler
- Creating a hybrid scheduler
- The ‘Update’ function for a hybrid scheduler.
- Reliability and safety issues
- The safest way to use the hybrid scheduler
- Other forms of co-operative scheduler
- PATTERN: 255-TICK SCHEDULER
- PATTERN: ONE-TASK SCHEDULER
- PATTERN: ONE-YEAR SCHEDULER
- PATTERN: STABLE SCHEDULER
- Mix and match
- Preparations for the next seminar
Seminar 3: Shared-clock schedulers for multi-processor systems
- Overview of this seminar
- Why use more than one processor?
- Additional CPU performance and hardware facilities
- The benefits of modular design
- The benefits of modular design
- So – how do we link more than one processor?
- Synchronising the clocks
- Synchronising the clocks – Slave nodes
- Transferring data
- Transferring data (Master to Slave)
- Transferring data (Slave to Master)
- Detecting network and node errors
- Detecting errors in the Slave(s)
- Detecting errors in the Master
- Handling errors detected by the Slave
- Handling errors detected by the Master
- Enter a safe state and shut down the network
- Reset the network
- Engage a backup Slave
- Why additional processors may not improve reliability
- Redundant networks do not guarantee increased reliability
- Replacing the human operator – implications
- Are multi-processor designs ever safe?
- Preparations for the next seminar
Seminar 4: Linking processors using RS-232 and RS-485 protocols
- Review: Shared-clock scheduling
- Overview of this seminar
- Review: What is ‘RS-232’?
- Review: Basic RS-232 Protocol
- Review: Transferring data to a PC using RS-232
- PATTERN: SCU SCHEDULER (LOCAL)
- The message structure
- Determining the required baud rate
- Node Hardware
- Network wiring
- Overall strengths and weaknesses
- PATTERN: SCU Scheduler (RS-232)
- PATTERN: SCU Scheduler (RS-485)
- RS-232 vs RS-485 [number of nodes]
- RS-232 vs RS-485 [range and baud rates]
- RS-232 vs RS-485 [cabling]
- RS-232 vs RS-485 [transceivers]
- Software considerations: enable inputs
- Overall strengths and weaknesses
- Example: Network with Max489 transceivers
- Preparations for the next seminar
Seminar 5: Linking processors using the Controller Area Network (CAN) bus
- Overview of this seminar
- PATTERN: SCC Scheduler
- What is CAN?
- CAN 1.0 vs. CAN 2.0
- Basic CAN vs. Full CAN
- Which microcontrollers have support for CAN?
- S-C scheduling over CAN
- The message structure – Tick messages
- The message structure – Ack messages
- Determining the required baud rate
- Transceivers for distributed networks
- Node wiring for distributed networks
- Hardware and wiring for local networks
- Software for the shared-clock CAN scheduler
- Overall strengths and weaknesses
- Example: Creating a CAN-based scheduler using the Infineon C515c
- Master Software
- Slave Software
- What about CAN without on-chip hardware support?
- Preparations for the next seminar
Seminar 6: Case study: Intruder alarm system using CAN
- Overview of this seminar
- Overview of the required system
- System Operation
- How many processors?
- The Controller node
- Patterns for the Controller node
- The Sensor / Sounder node
- Patterns for the Sensor / Sounder node
- Meeting legal requirements
- Processor decisions
- Hardware foundation
- Summary
- The code: Controller node (List of files)
- The code: Controller node (Main.c)
- The code: Controller node (Intruder.c)
- The code: Controller node (Sounder.c)
- The code: Controller node (SCC_m89S53.c)
- The code: Sensor / Sounder node (List of files)
- The code: Sensor / Sounder node (Main.c)
- The code: Sensor / Sounder node (Intruder.c)
- The code: Sensor / Sounder node (Sounder.c)
- The code: Sensor / Sounder node (SCC_s89S53.c)
- Preparations for the next seminar
Seminar 7: Processing sequences of analogue values
- Overview of this seminar
- PATTERN: One-Shot ADC
- Using a microcontroller with on-chip ADC
- Using an external parallel ADC
- Example: Using a Max150 ADC
- Using an external serial ADC
- Example: Using an external SPI ADC
- Example: Using an external I2C ADC
- Using a current-mode ADC?
- PATTERN: SEQUENTIAL ADC
- Key design stages
- Sample rate (monitoring and signal proc. apps)
- Sample rate (control systems)
- Determining the required bit rate
- Impact on the software architecture
- Example: Using the c515c internal ADC
- PATTERN: ADC PRE-AMP
- PATTERN: A-A FILTER
- Example: Speech-recognition system
- Alternative: „Over sampling”
- PATTERN: CURRENT SENSOR
- PWM revisited
- Software PWM
- Using Digital-to-Analogue Converters (DACs)
- Decisions …
- General implications for the software architecture
- Example: Speech playback using a 12-bit parallel DAC
- Example: Digital telephone system
- Preparations for the next seminar
Seminar 8: Applying „Proportional Integral Differential” (PID) control
- Overview of this seminar
- Why do we need closed-loop control?
- Closed-loop control
- What closed-loop algorithm should you use?
- What is PID control?
- A complete PID control implementation
- Another version
- Dealing with ‘windup’
- Choosing the controller parameters
- What sample rate?
- Hardware resource implications
- PID: Overall strengths and weaknesses
- Why open-loop controllers are still (sometimes) useful
- Limitations of PID control
- Example: Tuning the parameters of a cruise-control system
- Open-loop test
- Tuning the PID parameters: methodology
- First test
- Example: DC Motor Speed Control
- Alternative: Fuzzy control
- Preparations for the next seminar
Seminar 9: Case study: Automotive cruise control using PID and CAN
- Overview of this seminar
- Single-processor system: Overview
- Single-processor system: Code
- Multi-processor design: Overview
- Multi-processor design: Code (PID node)
- Multi-processor design: Code (Speed node)
- Multi-processor design: Code (Throttle node)
- Exploring the impact of network delays
- Example: Impact of network delays on the CCS system
- Preparations for the next seminar
Seminar 10: Improving system reliability using watchdog timers
- Overview of this seminar
- The watchdog analogy
- PATTERN: Watchdog Recovery
- Choice of hardware
- Time-based error detection
- Other uses for watchdog-induced resets
- Recovery behaviour
- Risk assessment
- The limitations of single-processor designs
- Time, time, time …
- Watchdogs: Overall strengths and weaknesses
- PATTERN: Scheduler Watchdog
- Selecting the overflow period – „hard” constraints
- Selecting the overflow period – „soft” constraints
- PATTERN: Program-Flow Watchdog
- Dealing with errors
- Hardware resource implications
- Speeding up the response
- PATTERN: Reset Recovery
- PATTERN: Fail-Silent Recovery
- Example: Fail-Silent behaviour in the Airbus A310
- Example: Fail-Silent behaviour in a steer-by-wire application
- PATTERN: Limp-Home Recovery
- Example: Limp-home behaviour in a steer-by-wire application
- PATTERN: Oscillator Watchdog
- Conclusions
- Acknowledgements
Bibliografie: