The course presents the circuits known as Field-Programmable Gate Array (FPGA) and that Complex Programmable Logic Device (CPLD), with the emphasis on the circuits of one of the representative manufacturers of such circuits, the company Xilinx.
It is assumed that the reader is familiar with the classic PLD type programmable circuits (such as PAL or GAL) also known as SPLD (Simple Programmable Logic Device).

What are FPGA and CPLD circuits?
Keeping the proportions we could say that the FPGA and CPLD circuits are the modern equivalent of the universal test boards (breadboard) on which were mounted simple digital circuits (gates, flip-flops, etc.) that could then be interconnected by wires by the user to test a specific application.
The statement will obviously be justified in the following. Before addressing the specific issue, the circuits known as Application-Specific Integrated Circuit (ASIC).
What are ASIC circuits?
ASIC is a complex integrated circuit dedicated to the implementation of a particular application, rather than a general use. An ASIC circuit is designed by a certain company and is made for a single beneficiary (client).
The exponential increase in the integration density of VLSI circuits makes it possible to integrate almost all of them under imaginable digital systems.
What does an ASIC circuit include?
An ASIC circuit may include a 32-bit microprocessor along with memory and complex peripherals, in which case it may also be referred to as a SoC (System on Chip) which means a calculation system made on a single microcircuit.
SoC is actually a very broad notion considering that among the peripherals can be included complex analog systems, MEMS type sensors (based on micro or nano mechanical technologies) and even high-performance radio frequency systems.
What are the differences between FPGA and ASIC?

A typical example of ASIC and SoC at the same time it is a circuit with which most of a mobile phone is made.
The arguments in favor of the SoC concept now resemble those that long ago justified the development of digital integrated circuits: reduced dimensions, reduced energy consumption and increased reliability compared to systems that used multiple components, reduced installation costs, all at once. another scale of complexity.
What are ASSP circuits?
Application Specific Standard Product (ASSP) it is also an integrated ASIC similar circuit dedicated to a certain application market, but intended for several users (hence "standard").
ASSP circuits are intended for several customers because they are of general use, but their number is small because the application is a specific one.
An important aspect related to ASIC circuits are the costs related to the preparation of the manufacture and partially to its design. Those costs are referred to as costs NRE (Non Recurring Engineering) they are usually very large (x 100000 USD) even for a purely numerical circuit so it is important to be sure that the application will be sold in a large volume so that these costs can be amortized.
Another aspect is that, in this case, the preparation of the technological manufacturing process regarding the (re) dimensioning of the silicon surface for ASIC type products takes a long time, so that the possible delays in launching the product on the market can reduce the profitability.
The numerical system in an ASIC
The numerical system in an ASIC which is also the most important under the system can be implemented through several technologies, depending on the required production scale.
For its realization are used as main technologies:
- fully dedicated circuits (full custom);
- standard cell circuits;
- FPGA circuit.
Bibliography:
https://www.xilinx.com/
https://twitter.com/XilinxInc
https://anysilicon.com/
http://indico.ictp.it
Nothing about Altera?
If you study the architectures of Altera and Xilinx chips, you will probably find the Altera chips more interesting.
Xilinx tends to be more technology-oriented and better connected to applications, offering more chips with customized circuits that implement specific functions.
But, an article about Altera will probably follow
I don't know if some of them are more interesting.
But I try, I'm struggling with a dizziness of Cyclone II, probably the cheapest and most expensive platform from Intel Altera, to which I added a JTAG interface - USB-Blaster and together with Quartus 9.1 or 13.0 I want to befriend them either under WIN 7, the first, or under WIN 8.1 the second software.
And the drivers are so… or heck he knows what, maybe even the USB-Blaster hard drive is to blame, that you can't help but get annoyed at every attempt.
I understand that there are no drivers available for Win7 or 8.1, or is there a problem with their operation, probably intermittent?
Drivers would be for 7 and 10. But win 8 and 8.1 are like that, the ostrich in terms of approaching drivers.
Although, in fact, 8.1 is a stable and balanced system. Don't give up too easily. Instead, the USB-Blaster fan from Altera, I think that's the mess.
It reminds me of Eminescu's lyrics: you see it (in the panel) and it's not! So yes, intermittently. Play black and white. It either detects it correctly or as an unknown device.
And when you think that everything is Intel .. From the platform, CPU, etc. and up to USB blaster, Altera ..
Interesting, however, if I were you I would try some things of curiosity. I would install a Win7 emulator via WMWare, or I would do a free update to Win10, which from my point of view is much more stable.
I have all 3 OS installed. I have already tried 7 and 8.1. With all the proposals received and the tricks I know.
I managed only once, on the 7th, to complete a project. A mini, a micro project: "Button-not-LED".
So the chain is good. But something in the driver-device area is rotten. I examined him physically. It's not. It's still soft. The ultimate goal is to implement a filter, most likely generated with matlab, maybe even with FDA Tools and exported to VHDL or verilog and then import it into Quartus.
And the test, buttons and LEDs. I don't think the tiny Cyclone 2 has CAN.
Interesting, do you communicate by serial or USB?
Windows PC -> USB -> Altera USB Blaster -> JTAG -> FPGA.
Altera USB Blaster programming module
Altera USB Blaster board attached.
Altera USB Blaster Card
Your USB blaster is a clone from my point of view. The original should say "Altera" not Altera-IC. Also, on the board (pcb) you do not see any component markings, a bit unusual for an original board. https://www.youtube.com/watch?v=FU2wybwDP1k
Yes, that's why I put the picture with the face, so that it can be seen that it is erased (scratched). But the original is not found.
From what I dug on the errors given by Windows when connecting the device, how much could be dug, the problem is the certificates.
My device does not deny its identity and this bothers Windows, which tells it to stop.
You connect it physically, it detects it, it asks who it is and who knows how my blaster responds to it because it gets upset and disconnects it and puts the lemon in the cpanel.
I think a safe solution here is either a hardware hack on the board, or an original module purchased (a newer version if possible).
Hard to understand if you are not at least at an average level with knowledge of digital electronics.
Agree. But as technology has evolved in the field of electronics, everyone working in the field should understand.
It's possible. I admit that, although I have some knowledge, I am not, I think, at the level to pronounce. There are probably other group colleagues who can do it.
FPGA and CPLD structures are the future. Processors have reached the limit in terms of technologies. Neither the frequencies nor the lithography help. The two major players in the processor market, Intel and AMD, did not pay big bucks without a clear strategy by purchasing the first Altera and the second Xilinx.
The two vectors that I see in the evolution of processors are, on the one hand, graphene / graphene technology, on the other hand, adaptive architectures. The processor that will self-configure according to the tasks assigned to it at a given time, using the maximum areas of structures, so that there are no downtime, long queues, bottlenecks, etc. The current major problem is the accelerations and decelerations that appear on the channels with the outside, the connecting buses with the peripherals.